1. Field of the Invention
The present invention relates to a multiplexed communication protocol for transmitting information between a central location and a plurality of similar distributed locations, and more particularly for transmitting interrupt, direct memory access (DMA) and other information between a central peripheral mounted on the system board of a multiprocessor computer system and a plurality of distributed peripherals associated with each microprocessor.
2. Description of the Related Art
The personal computer industry is evolving quickly due to the increasing demand for faster, smaller and more powerful computers. Modern computer systems are typically designed in modular form to achieve higher speed and power in as small a package as practical. In this manner, related functions are grouped together in single components and the components are connected together using several buses for transferring data between the components. As new capabilities are added or existing functions are enhanced or reorganized, the size and complexity of each of the components tends to increase. Consequently, the communication needs between the components becomes more complex and the number of input/output (I/O) signals increases, resulting in larger and more complicated bus structures.
The problems discussed above are prevalent in multiprocessor computer systems. Performance limits are being reached in single processor computer systems so that a major area of research in computer system architecture is multiprocessing. Multiprocessing involves a computer system which includes multiple processors that work in parallel on different problems or different parts of the same problem. The incorporation of several microprocessors significantly increases the complexity of a computer system. Consequently, the functions of the computer system are typically reorganized and new functions are added to solve contention problems between the processors. The addition and reorganization of functions creates the need for more sophisticated bus structures to provide efficient transfer of data.
For example, many functions that were centrally located in a single processor system may be distributed among the respective processors. Such distribution, however, often leads to a substantial increase in the number of I/O pins or signals between the central and distributed elements or components in a computer system. The width, or the number of signals residing on the respective buses, are significantly increased, resulting in larger and more expensive connectors when interfacing central and distributed functions. Also, the number of I/O pins on each device effects its size and packaging techniques. If gate arrays are used to implement the devices, larger die sizes and chips would be required to facilitate the increase in I/O pins.
It is desirable, therefore, to implement the necessary communication among central and distributed devices without significantly increasing the number of I/O pins or signals, and to allow smaller die sizes and chips and less number of signals residing on the buses.